1. Field of the Invention
The present invention relates to a large-capacity semiconductor memory device that has a structure similar to, for example, the structure of an eDRAM (embedded Dynamic Random Access Memory), wherein a plurality of memory blocks are mounted on a semiconductor substrate with respect to an I/O block.
2. Description of the Related Art
A large-capacity semiconductor memory device that is constructed, for example, like an eDRAM, which comprises an I/O block and a plurality of memory blocks, is called a large-capacity memory macro. A conventional large-capacity memory macro has a structure, for example, as shown in FIG. 17. In FIG. 17, a plurality of memory blocks 204<0> to 204<3> are connected to a DQB block 203, which is a data control unit, via local or complementary data lines DQt/c. The DQB block 203, in turn, is connected to an I/O block. Write data from outside is supplied as input data DIN. The write data is then delivered from the I/O block 201 to the DQB block 203. Subsequently, the write data is selectively written in any one of the memory blocks 204<0> to 204<3> via the data lines DQt/c. For example, in the case of an eDRAM, each memory block has a sense amplifier unit that is connected to the data lines DQt/c, and a memory array. Write data that is sent to the data lines DQt/c is written in the memory array by the sense amplifier unit. In addition, read-out data, which is selectively read out of any one of the memory blocks 204<0> to 204<3>, is delivered to the DQB block 203 over the data lines DQt/c. For example, in the case of the eDRAM, read-out data is read out from the memory array, which is included in the memory block, to the sense amplifier unit and is amplified. The amplified data is delivered to the DQB block over the data lines DQt/c. The read-out data, which has been read out to the DQB block 203, is re-amplified and is delivered to, and latched in, the I/O block. The latched data is output as output data DOUT.
In general, if the capacity of the memory macro increases, the length of data lines also increases, leading to a serious problem in the high-speed operation of the memory macro. It is thus imperative for the large-capacity memory macro to suppress an increase in data line length. In order to solve this problem, the data line control would become complex in many cases. The complex data line control will increase the circuit area of the DQB block and, as a result, the area of the memory macro will increase.